This invention relates to a semiconductor device, more particularly, a trench-type schottky-barrier diode (SBD), a method of manufacturing the device.
FIG. 1 is a sectional view showing the conventional trench-type schottky-barrier diode (SBD). As shown in FIG. 1, an N.sup.+ -type epitaxial layer 12 is formed on a surface of an N.sup.+ -type silicon substrate 11, and trenches 13 are formed in the N.sup.+ -type epitaxial layer 12. A P.sup.+ -type polysilicon layer 14 with high impurity concentration is formed, filling the trenches 13. On the surface of the epitaxial layer 12, a schottky metal 15 (anode electrode) is formed to cover the polysilicon layer 14. Provided on the other surface of the substrate 11 is an ohmic electrode (cathode electrode, not shown). A surface region 16 of the schottky metal 15 on the epitaxial layer 12 which is located between two polysilicon layers 14, functions as a diode operation region.
FIGS. 2A-2E are sectional views presented to serially show the manufacturing process of the conventional trench-type SBD shown in FIG. 1, i.e., from the step of forming the trenches to a step of forming the schottky metal. The reference numerals similar to those used in FIG. 1 designate like portions, for simplicity of illustration.
As shown in FIG. 2A, a CVD oxide film 17 about 400 nm thick is formed on the epitaxial layer 12 provided on the substrate 11 by the CVD (chemical vapor deposition). Using the subsequently patterned CVD oxide film as a mask, the trench 13 having an opening less than 2 .mu.m in width and depth is formed in the epitaxial layer 12 by means of the RIE (reactive ion etching). Then, the process for minimizing the damage to the side walls of the trench 13 (e.g. the process such as the wet etching with use of alkaline liquid) is performed. Next, an undoped polysilicon layer 18 of 800-1000 nm thick is formed by the CVD, filling the trench 13 as shown in FIG. 2B. FIG. 2C shows next that the undoped polysilicon layer 18 is etched back by the RIE to the same level as the surface of the epitaxial layer 12. Then, as shown in FIG. 2D, p-type impurity (boron) is doped into the undoped polysilicon layer 18 in the trench by use of the CVD oxide film mask used also in the trench forming step. Next, the device is subjected to a heating step, thereby the impurity doped into the undoped polysilicon layer 18 is diffused, as shown in FIG. 2E. By diffusing the impurity in this manner, a p-type polysilicon layer 14 is formed in the trench 13. Subsequently, a schottky metal 15 is formed by the sputtering, on the surfaces of the epitaxial layer 12 and the undoped polysilicon layer 14.
The above-mentioned structure, however, has some problems as described below. First, the undoped polysilicon layer 18 deposited in the trench by the CVD may damage the inner walls of the trench. The undoped polysilicon layer 18 is formed by the CVD and is inevitably rough-grained. Prior to the deposition of the undoped polysilicon layer, the epitaxial layer 12 forming the inner walls of the trench is considerably influenced by the RIE step for forming the trench 13. The influenced epitaxial layer is exposed to the deposition of such a rough-grained polysilicon layer, the interface between the epitaxial (i.e., the single crystalline) silicon and the deposited polysilicon will be inevitably affected adversely. This is the main cause of an increase in a leakage current generated during the operation of the device.
Secondly, a structural problem may arise. The smaller the device, the more difficult to secure a large operation region. As is clear from FIG. 1, when the diode operation region is desired to be formed to have a large area in a limited area having the trench, the width of the opening of the trench 13 is necessarily to be decreased. However, the trench opening cannot be decreased to be less than a specific limit. Therefore, the device cannot be made smaller without decreasing the operation region.
Thirdly, a problem exists also in the manufacturing process. The etch-back step of the undoped polysilicon layer 18 has to be controlled with considerably much care, otherwise the reliability of the device will decrease thereby. FIG. 2C shows that the polysilicon layer 18 is etched back to the level very near the surface of the epitaxial layer 12. However, the etch-back level can hardly be controlled well in such a manner. If the etch-back step ends in the condition where the level of the polysilicon layer 18 is extremely higher/lower than that of the epitaxial layer 12, some gaps may occur in the schottky metal 15 formed in the subsequent step.
As described above, in the conventional trench-type schottky-barrier diode, the leakage current generated due to the damage of the inner wall of the trench inevitably increase, and a large area of the operation region cannot be secured. Further, in order to attain high reliability, the manufacturing process has to be improved.